Mentor Graphics Catapult Synthesis 2021.1

The Catapult High-Level Synthesis Platform empowers designers to use industry-standard ANSI C++ and SystemC to describe functional intent and move up to a more productive abstraction level.The Catapult Synthesis line of products including the C Property Checker,Low Power option and Library Builder (LB).
• Catapult HLS is targeted for designing subsystems from timed SystemC or untimed C++ code.Catapult HLS enables subsystem design through multi-level hierarchy support and channel synthesis.
• Catapult Ultra extends the low power performance of designs created in Catapult HLS by integrating the RTL low power optimization capabilities directly into the Catapult design flow.
• Catapult Physical extends the functionality of Catapult Ultra with support for multi-voltage threshold libraries.
The Catapult® high-level synthesis tool empowers designers to use industry standard ANSI C++ and SystemC to describe functional intent, and move up to a more productive abstraction level. From these high-level descriptions Catapult generates production quality RTL. With this approach, full hierarchical systems comprised of both control blocks and algorithmic units are implemented automatically,eliminating the typical coding errors and bugs introduced by manual flows. By speeding time to RTL and automating the generation of bug free RTL, the Catapult significantly reduces the time to verified RTL.
Catapult’s unified flow for modeling, synthesizing, and verifying complex ASICs and FPGAs allows hardware designers to fully explore micro-architecture and interface options. Advanced power optimizations automatically provide significant reductions in dynamic power consumption. The highly interactive Catapult work flow provides full visibility and control of the synthesis process, enabling designers to rapidly converge upon the best implementation for performance, area, and power.
From these high-level descriptions, Catapult generates production-quality RTL. By speeding time to RTL and by automating the generation of bug free RTL, Catapult significantly reduces the time to verified RTL. The Catapult Platform pairs synthesis with the power of formal C property checking to find bugs early at the C/C++/SystemC level and to comprehensively verify source code before synthesis.
Catapult’s advanced power optimizations automatically provide significant reductions in dynamic power consumption. The highly-interactive Catapult workflow provides full visibility and control of the synthesis process, enabling designers to rapidly converge upon the best implementation for power, performance, and area.
The following sections describe the enhancements that were added in the current 2021.1 release.
• New pragma support
• Support for Conditional Pragmas
• Sample technology libraries removed
• New Flow for VSCode
• New Toolkit Examples
• Support for Xilinx Versal and Achronix Speedster7 Libraries
• C++ 14 support (Beta)
• Updated versions of AC DataTypes and PowerPro
• CFormal Apps for Idle Signal and Memory Dependency Verification (Beta)
• SLEC flow renamed to C Formal SLEC
• Updates to Design Analyzer